As integrated circuit devices become more highly integrated the fabrication process of these devices may become more difficult. For example, because the devices themselves have decreased in size, the space between the electrical wires in these devices as well as the width of the electrical wires themselves may decrease in size. Accordingly, contact holes that are formed between these wires have also been influenced, for example, contact holes may have a decreased diameter and/or increased depth. Contact holes of this nature are difficult to manufacture.
Contact holes having narrow diameters and increased depths, present in, for example, dynamic random access memory (DRAM) cells, may be formed using a self-aligned contact method. Typically, methods employing a self-aligned contact method do not require alignment of an etching mask. Further, using a self-aligned contact method may enable the manufacture of smaller contact holes without an additional alignment margin.
According to conventional methods of forming self-aligned contact holes, a plurality of first patterns are formed on the integrated circuit substrate. The first pattern typically includes a conductive layer pattern and a silicon nitride layer pattern formed on the conductive layer pattern. A nitride spacer is formed on a sidewall of the first pattern. An insulating layer is formed on the resulting structure by depositing silicon oxide on the surface of the resulting structure. A photoresist pattern is formed to expose portions of the first patterns. The insulating layer is anisotropically etched using the photoresist pattern as an etching mask to form a contact hole exposing a surface of the substrate between the first patterns.
According to conventional methods, depositing a conductive material in a contact hole may be difficult because the already small diameter of the hole may be decreased even further by the presence of a nitride spacer formed on the sidewall of the first pattern. One solution to this problem is to reduce the thickness of the nitride spacer to make room for the conductive material. However, reducing the thickness of the spacer such that there is space for the conductive material, may cause an electrical short to occur between the conductive layer pattern and conductive material deposited in the contact hole. This type of short is typically referred to as the bridge phenomenon and it typically occurs when the nitride spacer is too thin and, thus, etched through during subsequent etching processes.
Furthermore, since the spacer includes silicon nitride which has a dielectric constant of more than about 7 and the dielectric constant of an oxide layer has a dielectric constant of about 3.9, the parasitic capacitance of the first pattern may increase. When the parasitic capacitance increases, the response speed of the integrated circuit device may decrease during the operation thereof.
Solutions to the above identified problems with conventional fabrication methods have been attempted. For example, Japanese Patent Application Publication No. 11-168199 discusses a method wherein the contact hole is formed first and a spacer is formed on the inner side surface of the contact hole.
The method of manufacturing a DRAM discussed in the above referenced Japanese Patent Application will be discussed below with respect to FIGS. 1A to 1D. FIGS. 1A to 1D are cross sectional views illustrating conventional methods of manufacturing DRAM as discussed in the above referenced Japanese Patent Application.
Referring now to FIG. 1A, a first insulating layer 12 comprising, for example, a silicon oxide layer, is formed on an integrated circuit substrate 10. A gate oxide layer (not shown) and gate electrode (not shown) are formed on the integrated circuit substrate. Conductive patterns 14 that function as bit lines are formed on the first insulating layer 12. A second insulating layer 16 and a third insulating layer 18 are sequentially deposited on the surface of the resulting structure. The second insulating layer 16 is typically formed of silicon oxide and the third insulating layer 18 is typically formed of silicon nitride.
Referring now to FIG. 1B, a first contact hole 20 is formed to expose a portion of the integrated circuit substrate 10. A photoresist pattern is formed on the third insulating layer 18. The third 18, second 16 and first 12 insulating layers are sequentially etched using the photoresist pattern as an etching mask, such that a first contact hole 20 is formed that exposes at least a portion of the integrated circuit substrate 10.
Referring now to FIG 1C, a spacer 22 is formed on a sidewall of the first contact hole 20. In particular, a silicon oxide layer is deposited on the third insulating layer 18 and in the first contact hole 20 (FIG. 1B). The silicon oxide layer is anisotropically etched to form a spacer 22 on the sidewalls of the first contact hole 20.
Referring now to FIG. 1D, a capacitor electrode is formed on the integrated circuit substrate 10. In particular, a conductive material is deposited to a predetermined thickness on the third insulating layer 18, in the contact hole 20 and on the spacer 22. The conductive material is patterned to form a stacked storage electrode 24. A dielectric layer 26 and a plate electrode 28 are sequentially formed on the storage electrode 24, thereby completing the capacitor electrode, the spacer 22 insulating the storage electrode 24 from the conductive pattern 14.
According to conventional methods of fabricating DRAMs discussed above, the area of the bottom of the first contact hole 20 is enlarged because the first contact hole 20 is formed prior to the formation of the spacer 22. In addition, the parasitic capacitance of the conductive pattern decreases since the spacer 22 is formed using silicon oxide.
However, when the contact hole 20 is small in diameter and/or deep, the conventional methods may present a problem. For example, since the storage electrode 24 has a stacked shape, enlargement of an area of the storage electrode 24 is limited and, therefore, a capacitance of the capacitor may decrease. Furthermore, if the sidewall of the first contact hole 20 is formed to have a step, the silicon oxide layer may not be deposited uniformly, which may result in the bridge phenomenon between the conductive pattern 14 and the storage electrode 24.
In the above-mentioned fabrication methods of DRAM, one or more cylindrical storage nodes may be formed so as to enlarge the surface area of the storage electrode 24.
Now referring to FIGS. 2A and 2B, cross sectional views illustrating fabrication of conventional DRAM cells including a cylindrical storage node will be discussed. As illustrated in FIG. 2A, a conductive material is deposited in the first contact hole (20 in FIG. 1B) to form a conductive plug 40. An oxide layer 42 is deposited on the surface of the conductive plug 40. A predetermined portion of the oxide layer 42 is etched away forming a second contact hole 44 that partially exposes the conductive plug 40. The cylindrical storage node 46 is formed in the second contact hole 44.
However, if the second contact hole 44 is formed without being precisely aligned with the conductive plug 40 disposed below the second contact hole 44, the oxide layer 42 may be over etched and the spacer 12 disposed on the side of the conductive pattern 14 may be accidentally etched away as illustrated by the broken lines in FIG. 2B. The spacer 12 may be accidentally etched because the spacer 22 and the oxide layer 40 have similar etching rates. Accordingly, a pattern bridge (an electrical connection) may occur between the conductive pattern 14 (functioning as bit line) and the storage electrode 48 and the integrated circuit device may not function correctly or at all.